Teaching

The course covers the design, implementation, and verification of digital hardware systems using a hardware description language. It begins with the fundamentals of SystemVerilog and the register-transfer level (RTL) design abstraction, then builds up the core structural elements of a digital system: compute datapaths, control finite-state machines (FSMs), memory elements, and latency-insensitive interfaces. The course next examines how a design is analyzed and optimized against quality metrics (e.g., resource usage, throughput, latency, power consumption) by covering topics such as pipelining, resource sharing, static timing analysis, and interconnect delay. It closes with an introduction to FPGA architecture and how RTL designs map onto the underlying hardware. Functional verification using SystemVerilog testbenches and waveform-based debugging is addressed throughout the course. Students apply this material in a sequence of four labs that use a commercial FPGA tool suite (AMD/Xilinx Vivado) and require deploying and demonstrating working circuits on an FPGA board, supported by weekly tutorials. Course prerequisites are introductory digital logic design (ECE 124 or equivalent) and basic programming skills.

The course dives into the design and implementation of specialized computer hardware systems for machine learning (ML) workloads. It begins with a brief overview of common ML workloads and their compute/memory characteristics. Then, it covers architectural and microarchitectural details of key components of a custom ML acceleration chip through examples of several commercial accelerators. The course next examines model-hardware co-design principles for efficient ML compute (e.g., pruning, quantization, knowledge distillation, hardware-aware neural architecture search). It closes with an introduction to compiler infrastructure for ML hardware and discusses the ML-driven architecture evolution of general-purpose compute platforms, such as GPUs and FPGAs. Aspects related to large-scale distributed ML deployments and the hardware/software stack for large language model (LLM) serving may also be addressed. During this course, students will engage with recent research in this area through paper readings, guest lectures from industry speakers, labs that provide them with hands-on experience using commercial accelerators, and a major team project component. Course prerequisites are RTL digital design (ECE 327 or equivalent) and basic programming skills. Background in computer architecture or ML theory/applications is not required but would be helpful.