Andrew Boutros
Assistant Professor · Electrical & Computer Engineering · University of Waterloo
I am an Assistant Professor of Electrical and Computer Engineering at the University of Waterloo. My research focuses on building reconfigurable computing architectures that are more efficient, easier and faster to program, and better suited for demanding workloads at the edge and in datacenters. My work spans architecture and circuit modeling, computer-aided design tools, and application–hardware co-design.
Before joining Waterloo, I received my PhD in Electrical and Computer Engineering from the University of Toronto, where I was lucky to be trained by Vaughn Betz. During and before my PhD, I was a researcher at Intel Labs and Intel's Programmable Solutions Group, now Altera. I later established and led the Toronto office of MangoBoost, a startup developing data-processing units for datacenter infrastructure acceleration.
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Recent news
- Three full papers on DSP block modifications for MXFP formats, modeling of multi-die FPGA routing, and automatic generation of hardware parsers were accepted for publication at FPL 2026.
- Two full papers on automatic placement and routing for AI engines and optimizing VPR packing runtime were accepted for publication at FCCM 2026.
- Our FPL 2025 Double Duty paper, which proposes architecture modifications that allow the concurrent use of FPGA lookup tables and adder chains, won the Best Paper Award.
- Our work on FPGA logic block modifications that enable the concurrent use of lookup tables and hardened carry chains was accepted for publication at FPL 2025.
- Our VTR 9 paper was accepted for publication in ACM TRETS.
- I started my new role as a tenure-track Assistant Professor at the University of Waterloo.
- I passed my PhD final oral examination, wrapping up my graduate-school experience.
- I announced that I would join the University of Waterloo ECE department as a tenure-track Assistant Professor in January 2025.
- I passed my PhD departmental oral examination.
- Our work on using FPGA software-programmable overlays to accelerate graph neural network inference was accepted for publication at FPL 2024.
- Our work on FPGA-based graph neural network acceleration was accepted for a poster presentation at FCCM 2024.
- George Constantinides, Christos-Savvas Bouganis, and I organized the SpatialML Workshop at ISFPGA 2024.
- Our FPT 2023 paper on 3D-stacked reconfigurable acceleration devices won the Best Paper Award.
- Our work on 3D-stacked reconfigurable acceleration devices was accepted for publication at FPT 2023.
- Our work on the architecture exploration flow of future reconfigurable acceleration devices was accepted for publication at FPL 2023.
- Our book chapter on FPGA architecture was published in Springer Nature's Handbook of Computer Architecture.
- Our work extending the Koios suite of deep-learning FPGA benchmark circuits was accepted for publication in IEEE TCAD.
- Our work on placement optimization for FPGAs with embedded hard networks-on-chip was accepted as a full paper at FCCM 2023.
- Our work on flexible FPGA-based acceleration of natural-language models, including BERT and GPT, was accepted for publication in ACM TACO.
- Our journal paper on architecture and application co-design for new beyond-FPGA devices was accepted for publication in IEEE Access.
- Our paper on FPGA SmartNICs for AI training was accepted for publication in IEEE Computer Architecture Letters.
- Our paper on architecture exploration for novel beyond-FPGA reconfigurable acceleration devices was accepted for publication at FPL 2022.
- Our paper on specializing AI FPGA overlays won one of the Best Paper Awards at ICM 2021.
- Our work on specializing AI overlays for target workloads was accepted for publication at ICM 2021.
- Our survey on the principles and progression of FPGA architecture was published in IEEE Circuits and Systems Magazine.
- Two full papers were accepted for publication at FPL 2021.
- Our work on the Stratix 10 NX neural processing unit was featured on Intel's Stratix 10 NX webpage and in an Intel white paper.
- Our work on enhancing FPGAs with in-BRAM compute for deep learning was accepted as a full paper at FCCM 2021.
- Our paper on deep-learning security in multi-tenant cloud FPGAs was nominated for the Best Paper Award at FPT 2020.
- Two full papers were accepted for publication at FPT 2020.
- Our work on optimizing FPGA logic blocks for deep-learning arithmetic was accepted for publication in ACM TRETS.
- I was selected as one of 22 post-graduate affiliates across Canada in the Vector Institute's 2020 cohort (announcement).
- Our work on multi-FPGA acceleration of neural machine translation was accepted for publication at FPT 2019.
- Our work on FPGA and ASIC integration for persistent recurrent neural networks was accepted for publication at FCCM 2019.
- Our work on FPGA logic blocks for low-precision deep learning was accepted for publication at FPGA 2019.
- Our work on evaluating and enhancing Intel Stratix 10 FPGAs for persistent AI was accepted for a poster presentation at FPGA 2019.
- Our paper on low-precision DSP blocks for deep learning won the S. Vassiliadis Best Paper Award at FPL 2018.
- I successfully defended my MASc thesis, Enhancing FPGA Architecture for Efficient Deep Learning Inference.
- Our work on quantifying the efficiency gap between FPGA and ASIC convolutional neural network accelerators was accepted for publication in ACM TRETS.
- Our work on low-precision DSP blocks for deep learning was accepted for publication at FPL 2018.
- I received the University of Toronto Right Track CAD Graduate Scholarship for research excellence in programmable logic.
- I joined the Vector Institute as a post-graduate affiliate in its 2018 cohort (announcement).
Selected publications
A complete list is available on the publications page.